The present invention relates to integrated-circuit memory arrays, and in particular, to sensing of currents during reading of such memory arrays to determine the value of a logic level stored in a memory cell of the memory array.
Sense amplifiers are typically used to read the state of memory cells in a memory array, such as read-only memory (ROM) arrays, programmable read-only memory (PROM) arrays, and erasable programmable read-only memory (EPROM) arrays, among others. A memory cell typically stores charge to indicate the logic state of the memory cell. The logic state might be binary (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) or might be multi-level for higher order logic. A typical ROM array may contain millions of memory cells, typically arranged in rows and columns. Some memory arrays use floating-gate field-effect transistors (FETs) as the memory cell device, with the sources of each cell in a column being connected to a source-column line, and the source-column line for a selected cell may be connected to a reference voltage or ground (zero voltage) when the selected cell is read by the sense amplifier.
The drains of each cell in a column are connected to a separate bit-line (drain-column line), and the drain-column line for a selected cell is connected to the input of the sense amplifier when the selected cell is read. The control gates of each cell in a row are connected to a word line, and the word line for a selected cell is connected to the predetermined select voltage during reading of the selected cell. When the cell is read, the current through the selected cell is compared to a reference current to determine whether the selected cell is programmed with a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d.
In some conventional devices, the reference circuitry is connected to the input of a current-sensing amplifier and the output of this current-sensing amplifier is connected to one input of a differential amplifier. The differential amplifier compares the voltage output of the current-sensing amplifier with the voltage output of a second current-sensing amplifier connected to the memory cell being read. The reference current is typically chosen to provide a clear indication of the memory cell state being read.
However, errors in reading the state of the memory cell can arise. One of the problems encountered when using sense amplifiers is that the capacitance of the drain-column line can affect the initial current from the sense amplifier. These current surges can cause an error in reading the true state of the memory cell if sufficient time is not allowed for the drain-column line to settle. Providing sufficient settling time for a worst-case scenario slows operation of the memory array, which is undesirable, especially if the memory array is desired to be used with a fast microprocessor.
Pre-charging the drain-column line is one way to avoid the settling time associated with in-rush current, but pre-charging may have undesirable effects as well. While the use of pre-charge circuitry can improve access time, conventional pre-charge circuits can draw a large amount of current from the voltage supply. Pre-charging can also introduce timing issues. The pre-charging should be on long enough to insure that the drain-column line is sufficiently charged to avoid data sensing errors, but not so long as to unduly slow operation of the memory array.
Some of the chip area and current draw required by pre-charge circuitry can be at least partially offset by eliminating the differential amplifier used in two-stage sense circuits. In one single-stage sense amplifier, the output of the sense amplifier is set to a default state (e.g. the xe2x80x9c0xe2x80x9d state). The output only needs to be set if it is not the same as the default output value, thus the sensing margin can be improved. When the default data is xe2x80x9c0xe2x80x9d, the sensing speed can be limited by the cell current. If the cell current is large, data xe2x80x9c1xe2x80x9d speed is fast, but if the cell current is low, then data xe2x80x9c1xe2x80x9d speed is slower. Different cells in the memory array may provide different cell currents when read, so it may be necessary to provide a read period sufficient for the lowest cell current.
Timing of the pre-charge cycle can be simplified if the pre-charging is automatically stopped when the desired default value is reached. One pre-charge circuit uses a pair of series-connected FETs between a positive bias voltage supply and the data line with the output of the sensing amplifier being connected between the FETs. The FETs are gated with the inverse of the input value, in other words, when the input value is low, the gate voltage is high, and the FETs turn on and supply the output node with current from the positive voltage supply. When the input value is high, the gate voltage is low, and the FETs turn off, blocking the current path from the voltage supply. However, the the threshold voltage of the first (precharge) transistor is chosen so that, when the FETs are on, the precharge transistor has a low conductivity channel with respect to the second (pass) transistor. When the input value is low, the FETs are turned on and the output is pulled low. When the input value is high, a depletion-mode FET with the gate connected to the output is provided between the positive supply and the output of the sense amplifier to provide current from the positive voltage supply to the sense amplifier output and pull the output to a high state.
However, the series-connected FETs are relatively large in order to efficiently pre-charge the output, and this loads the gate bias circuit, slowing operation. Similarly, the depletion-mode pull-up transistor loads the sense amplifier output, which is also undesirable. In this type of circuit, the output of the sense amplifier tracks the data level, offset by about 200 mV higher than the data level. This may not be the optimum voltage for the next stage, which is typically an inverter and latch with a complementary metal-oxide-semiconductor (CMOS) circuit that might draw leakage current if not properly biased off.
The problems associated with using a depletion-mode FET between the output and the positive voltage supply have been addressed by using a diode-connected p-channel FET with the gate connected to the output of the sense amplifier. The level of the output swing can be reduced, but the output level still might not be appropriate for the next stage, and current may be drawn through the next stage, even in stand-by mode. Thus, there is a need to develop a sense amplifier with a pre-charge path that automatically shuts when the proper value is reached, and produces a value consistent with the stage following the sense amplifier. It is further desirable that the sense amplifier be low power, have a small layout area, and have improved sensing speed.
Sense amplifiers according to the present invention automatically shut down the pre-charge path before sensing the bit value by controlling a precharge path with an inverted output signal. The default data condition is a low Vt state, thus avoiding pre-charging the bit line high before going low when reading a low threshold (conductive) cell. In one embodiment, a pull-up path is provided by a p-channel MOSFET with the gate connected to ground to avoid DC leakage through the CMOS data latch in standby mode. The ground connection also provides an essentially constant VGS, unlike diode-connected pull-up transistors.
Sense amplifiers generally have an input node capable of being connected to a bit line of a memory array with a pass transistor connected between the input node (data line) and an output node. According to one embodiment of the present invention, an inverter inverts the signal at the output node and provides the inverted signal to the gate of a precharge transistor. The precharge supplies current from the supply (VDD) to the output node. The combination of the inverter and the pre-charge transistor pre-charges the output to a level just below the flip level of the following sensing inverter of the data latch stage when the sense amplifier is enabled.
If the data cell is in a conductive (xe2x80x9c1xe2x80x9d) state, the pass transistor turns on and the output is maintained at essentially the pre-charge level during the data latch period. If the data cell is in a non-conductive (xe2x80x9c0xe2x80x9d) state, the pass transistor is turned off and the output is pulled up over the flip level of the sensing inverter by the pull-up transistor that couples the output node to VDD. This pull-up period is short because the pre-charge level is close to the flip level of the next stage.
In a particular embodiment a sense amplifier having an input node configured to be connected to a bit line of a memory array includes a pass transistor with a first pass conduction terminal connected to the input node and a second pass conduction terminal connected to an output node. An inverter with its input coupled to the output node provides a pre-charge bias voltage at an inverter output. The inverter output is coupled to a control terminal of a pre-charge transistor. A first conduction terminal of the pre-charge transistor is configured to be connected to a voltage supply providing a bias voltage, and a second conduction terminal of the pre-charge transistor is connected to the output node. A pull-up transistor has a first pull-up conduction terminal configured to be connected to the voltage supply and a second conduction terminal connected to the output node.
In some embodiments the sensing inverter of the latch stage is used to invert and feedback the data output through the pre-charge transistor. In other embodiments, a separate inverter is supplied. In either instance, the pre-charge level is set below but close to the flip level of the inverter. In a further embodiment, a diode connection is provided in a CMOS inverter in the data latch circuit to avoid DC current draw when the sense amplifier is in standby.
In one embodiment, a sense amplifier having an input node configured to be connected to a bit line of a memory array includes a pass transistor having a first pass conduction terminal connected to the input node and a second pass conduction terminal connected to an output node. An inverter has its input coupled to the output node and provides an inverter output to a control terminal of a pre-charge transistor. A first conduction terminal of the pre-charge transistor is configured to be connected to a voltage supply providing a bias voltage, and a second conduction terminal is connected to the output node. A pull-up transistor has a first pull-up conduction terminal configured to be connected to the voltage supply and a second pull-up conduction terminal connected to the output node. The gate terminal of the pull-up transistor connected to a ground potential. A latch circuit having a second inverter including a complementary pair of transistors with a common control node is coupled to the inverter output. A diode connection is connected in series with the complementary pair of transistors between the voltage supply and the ground potential